The present invention relates to flash memory semiconductor devices. More particularly, the present invention relates to 0.18-xcexcm flash memory semiconductor devices. Even more particularly, the present invention relates to eliminating voids in the interlayer dielectric material of 0.18-xcexcm flash memory semiconductor devices.
Currently, the semiconductor industry is experiencing shorting problems associated with the silicon (Si) of a CS59 0.18-mm flash memory technology device coming in contact with a tungsten plug due to void formation within the interlayer dielectric (ILD0) boron phosphorous tetraethylorthosilicate (BPTEOS) layer. Void formation has been found to be especially prevalent between drain contacts in related art devices. FIG. 1 is a scanning electron micrograph (SEM) of such a device, in cross-section, demonstrating such void 10 formation along a xe2x80x9cword linexe2x80x9d direction between the drain contacts 11, in accordance with the related art. FIG. 2 is another SEM illustrating, at higher magnification, a device cross-section in which a barrier metal deposition (BMD)/tungsten material 12 from a plug has extended into the voids 10 formed in the ILD, thereby shorting the neighboring drain contacts 11, as experienced in the related art devices. Although boron-phosphorous-silica (BPxe2x80x94SiO2) films, having a relatively high density, have been deposited using a lower deposition rate, a method for forming BPTEOS films using a lower deposition rate has not been known to the Applicants before their invention. Therefore, a need exists for providing a method of eliminating voids in the interlayer dielectric material of 0.18-xcexcm flash memory semiconductor devices and a device thereby formed.
Accordingly, the present invention provides a method of eliminating voids in the interlayer dielectric material of 0.18-xcexcm flash memory semiconductor devices and a voidless device thereby formed. More specifically, the present invention provides a method for eliminating voids in the interlayer dielectric material of a 0.18-xcexcm flash memory semiconductor device by providing a first BPTEOS layer being formed by using a very low deposition rate and having a thickness in a range of approximately 3 kxc3x85; and providing a second BPTEOS layer being formed by using a standard deposition rate and having a thickness in a range of approximately 13 kxc3x85, wherein both layers have an atomic dopant concentration of approximately 4.5% boron (B) from triethylborate (TEB: C6H15O3B) and approximately 5% phosphorous (P) from triethylphosphate (TEPO: C6H15O4P).
This two-step deposition process completely eliminates voids in the ILD layer for a 0.5-xcexcm distance (gate-to-gate) as well as 0.38-xcexcm distance (gate-to-gate) which is the future flash technology. A low deposition rate such as 8xc2x12 xc3x85/sec is driven by a combination of low flow rates of the precursor materials of B and P dopants and tetraethyl orthosilicate (TEOS; i.e., Si(OC2H5)4). Particularly, a low dopant/TEOS flow (e.g., TEB at 60 g/minxc2x130% TEPO at 30 g/minxc2x130%, TEOS at 200 g/minxc2x130%) performed at a higher pressure (e.g., 450xc2x1250 Torr) during the deposition of the first layer provides an excellent gap-filling capability which eliminates voiding. The second BPTEOS layer may be deposited at a higher deposition rate such as 100xc2x110 xc3x85/sec. Further, the present invention has the advantage of in-situ deposition of the void-free ILD0 layer of the 0.18-xcexcm flash memory semiconductor device having a sound dopant concentration by preventing crystallization of boron phosphate (BPO4) and maintaining the xe2x80x9cC1xe2x80x9d etch process using existing tools such as a heat lamp.